Generally, the integrated circuit (IC) industry is continually attempting to improve the frequency of operation and performance of integrated circuits (ICs) while simultaneously attempting to add new functionality and features to these same integrated circuits (ICs). In order to improve performance while simultaneously increasing functionality, many different fabrication and packaging techniques are now being utilized or proposed for use in the IC industry. Some common prior art structures 10, 14, 16, and 18 which are believed to generally increase the performance of electrical systems and generally improve the functionality of integrated circuits are illustrated in FIGS. 1-4.
FIG. 1 illustrates one type of silicon-on-silicon (SOS) prior art device 10 which has been used or proposed for use in the IC industry. The SOS device 10 contains a large first integrated circuit 20 and a smaller second integrated circuit 22. The first integrated circuit 20 has two concentric peripheral rings of bond pads 24b and 24a with the pads 24b lying within the ring of pads 24a. The integrated circuit 22, which is an integrated circuit having a footprint much smaller than integrated circuit 20, has at least one ring of peripheral bond pads 26 around its periphery. The smaller integrated circuit 22 is placed on top of a central portion of the integrated circuit 20 as in FIG. 1. The bond pads 24b of integrated circuit 20 are then wire bonded to the bond pads 26 of integrated circuit 22 as illustrated in FIG. 1. The wire bonds coupled between the pads 24b and 26 allow for electrical circuitry on the integrated circuit 22 to communicate with electrical circuitry located on the integrated circuit 20. In addition, external terminals of an IC package, that are not illustrated specifically in FIG. 1, are wire bonded to the bond pads 24a of IC 20 in FIG. 1. Some bond pads 24b are selectively connected to some bond pads 24a to allow the IC 22 to connect to external package terminals. Therefore, the bond pads 24a in FIG. 1 allow both integrated circuits 20 and 22 to communicate with each other and communicate with an external environment that contains a larger electrical system.
The structure of FIG. 1 suffers from many disadvantages. First, electrical signals must be routed from active circuitry on a top active surface of the integrated circuit 22 to a peripheral portion of the integrated circuit 22 which contains the pads 26. Many IC dies can be the size of a postage stamp or the size of a human fingernail whereby this on-chip routing length on IC 22 alone is significant and performance-limiting. Once this on-chip routing is performed on a surface of IC 22, the wire bond from the bond pads 26 to the bond pads 24b is needed in order to connect electrical circuitry on the IC 22 to both the IC 20 and external package terminals. Therefore, these wire bonds will add another centimeter or so in wire length to the metallic routing of one or more IC signals in FIG. 1.
In addition to the above routing lengths, additional metallic routing must be performed between the bond pads 24b, active circuitry on the integrated circuit 20, active circuitry on IC 22, and bond pads 24a in FIG. 1. This additional routing serially adds more routing length to one or more already long routing paths previously discussed. Finally, yet another long wire bond connection is needed to connect integrated circuits 20 and 22 to the external terminals. These long routing interconnections in FIG. 1 will have increased resistance (R), increased inductance (I), and increased capacitance (C) than most other conventional IC connections. Due to these increased electrical characteristics between and around the ICs of FIG. 1, many high performance IC products (e.g., products having a desired operation at or above a few hundred mega Hertz (MHz) may not meet timing specifications and may be frequency limited.
In addition, noise and bandwidth problems occur along the longer routing paths that are required for some electrical signals in the structure of FIG. 1. The increased parasitics will require that input and output drivers/receivers on the integrated circuits 20 and/or 22 be increased in size and strength which will then increase integrated circuit sizes and complexity. Furthermore, the maximal number of inputs/outputs of the device of FIG. 1 is limited since inputs and outputs can only be connected from a periphery of the circuit 20 which is limited linearly in number by IC area. The longer connection paths of FIG. 1 will also not be able to supply proper power and dynamic current to the active circuitry of integrated circuits 20 and 22 whereby modern devices that consume on the order of tens of watts of power may not adequately be supplied with functional power and ground signals without adverse heating. In addition, the interconnection scheme utilized in FIG. 1 may limit architectural freedom, whereby system designers may not be able to optimally design system architectures in a manner to continue the current trend of doubling IC performance enhancement roughly every 1.5 years. In general, the increased parasitics associated with the long connection lengths ICs and terminals in FIG. 1 is unacceptable for many high performance systems. Shorter critical interconnect lengths need to be obtained in a new package design.
In an attempt to create a more compact device than that illustrated in FIG. 1, yet another silicon-on-silicon (SOS) device 12 was developed or proposed for use as illustrated in FIG. 2. In FIG. 2, three integrated circuits 30, 32, and 34 are stacked on top of one another with the active surface of each IC facing upward in FIG. 2. The integrated circuit 30 contains bond pads and tape automated bonding (TAB) portions 42 which electrically couple to active circuitry on the circuit 30. The integrated circuit 32 also contains conductive tab portions 40 in FIG. 2 which allows the IC active circuitry of circuit 32 to electrically interface to an external system or to other ICs 34 and 30. In a similar manner, integrated circuit 34 in FIG. 2 is electrically coupled to the conductive tab regions 38. All three integrated circuits 30, 32, 34 are then encapsulated by material 36 whereby the material 36 exposes the conductive tab portions 38, 40, 42 so that these tab portions may be three-dimensionally connected to conductive traces on planar printed circuit board (using a complex three dimensional wiring process or a complex and expensive special-purpose socket).
The package illustrated on FIG. 2 is an incredibly complex and expensive package to manufacture and design into a circuit board, and for this reason alone is prohibitive. In addition, even though a more compact semiconductor structure can be formed in FIG. 2 when compared to a solution that uses the configuration of FIG. 1, the package of FIG. 2 still suffers from many of the disadvantages discussed previously with respect to the SOS device of FIG. 1. In other words, the design of FIG. 2 still contains long routing paths between active circuitry and other integrated circuits within the packaged device where resistance, inductance, and capacitance are increased while frequency of operation and speed are typically decreased. The drivers for the active devices in FIG. 2 also need to be increased in size in order to handle the increased parasitics of these long interconnections. The same signal power and signal noise problems result as previously discussed, and the design of FIG. 2 is also pad-limited, as is the circuitry of FIG. 1, due to peripheral pad configurations. In general, while the design of FIG. 2 may enable placement of more functionality in a smaller spatial area than the structure of FIG. 1, the design of FIG. 2 still suffers from many of the disadvantages encountered by the design 10 in FIG. 1.
The integrated circuit (IC) industry has begun to use multi-chip modules (MCMs) in order to integrate more functionality into a single semiconductor package. One such example is one of the package configurations of the Pentium TM Pro product from Intel Corporation (Santa Clara, Calif. FIG. 3 illustrates a single multi-chip module (MCM) 16 which contains two integrated circuits 52 and 54 laterally adjacent one another in a semiconductor package 50. The integrated circuit 52 of FIG. 3 contains bond pads 56 and the integrated circuit 54 of FIG. 3 contains bond pads 58. These bond pads 56 and 58 connect to active devices on their respective ICs 52 and 54. These bond pads may either be used to couple active circuitry from one or more of the integrated circuits 52 and 54 to external pins of the package 50, or may be used to interconnect active circuitry from integrated circuit 52 to active circuitry on integrated circuit 54 via the package-contained metallic interconnect regions 60 in FIG. 3.
While the MCM module 16 allows more integrated circuits to be packaged in a single semiconductor package, the multi-chip module 16 of FIG. 3 still suffers from the parasitic and routing problems previously illustrated for FIGS. 1 and 2. In fact, the parasitics for the device in FIG. 3 are most likely worse than the parasitics for the devices in FIGS. 1-2. A further disadvantage is that the multi-chip module 16 of FIG. 3 is not a vertically stacked three-dimensional structure as are the devices of FIGS. 1-2. Due to this lacking feature, the two-dimensional footprint of the device 16 of FIG. 3 is greatly increased over the footprint of the devices illustrated in FIGS. 1 and 2. Therefore, when using the device of FIG. 3, the overall surface of system-level printed circuit boards which contain the device of FIG. 3 must be increased in surface size to accommodate the MCM components.
FIG. 4 illustrates another manner in which the integrated circuit (IC) industry is attempting to integrate more functionality into a smaller physical space. FIG. 4 illustrates a highly integrated chip (HIC) 18. In order to obtain more functionality in a smaller area, the integrated circuit industry is attempting to integrate many different types of structures, process steps, and functions onto a single large integrated circuit (IC) die. HIC devices may integrate many different types of IC modules into a mixed-technology device. FIG. 4 illustrates one theoretical possibility of a digital signal processor (DSP) core 62, a microprocessor 64, an analog to digital (A/D) converter 66, bipolar power logic 72, dynamic random access memory (DRAM) 68, and electrically erasable programmable read only memory (EEPROM) 70 all integrated onto a same contiguous integrated circuit substrate.
By integrating all of the two-dimensional circuit modules of FIG. 4 onto a single non-segmented two-dimensional substrate, the physical dimensions of the entire integrated circuit of FIG. 4 is very large. It is well known that larger integrated circuits are more likely to encompass some sort of silicon defect or be more likely to be affected by a process anomaly than smaller-sized ICs. Therefore, larger integrated circuits will typically yield at a much lower yield percentage than a composite of segmented and smaller integrated circuits. Therefore, the cost of manufacture of these HIC devices is very large, and the scrap percentage of the products illustrated in FIG. 4 is usually prohibitive. To avoid these problems, complex redundancy or complex error-correcting system architectures are needed which is also prohibitive.
Furthermore, the process technology required to manufacture, for example, a digital signal processor is very different from a process needed to manufacture, for example, a memory device (e.g., a DRAM or an EEPROM). Since all of these different technologies which usually require very different processes are now integrated on a single integrated circuit, compatibility issues between the different technologies and processes may render integration incredibly difficult, if not impossible. As an example, the device of FIG. 4 is probably too large, too complex, and too integrated to be manufactured even today using the most advanced and highly integrated process currently known. In addition, the structure of FIG. 4 still suffers from some of the parasitic problems discussed previously for FIGS. 1-3. For example, if the processor 64 requires some communication with the power logic 72, a large length of substrate surface area must be traversed by electrical signals before communications between these two diagonal and distant components can take place. The timing, power, routing, parasitics, etc. of these long connections is problematic both electrically and when designing the product using current computer aided design (CAD) tools. Therefore, the two-dimensional structure of FIG. 4 is limiting in a manner similar to that previously discussed for FIGS. 1-3 and even has added disadvantages as discussed hereinabove.
Therefore, a need exists in the industry for a new multi-chip device which can reduce the interconnect lengths of metal and reduce the adverse effects of routing parasitics. In addition, this new package should accomplish one or more of reducing driver size and or integrated circuit (IC) footprint area, improving power supply robustness to the MCM integrated circuits, reduce signal noise, improve product yields, result in simpler fabrication processes to enable enhanced yield, increase input and output signal counts of integrated products, enable more flexible system architectures and designs, reduce IC power consumption, enable lower power supply voltages, reduce conductive interconnect lengths, and/or reduce speed critical paths within integrated circuit (IC) architectures.